1. Field of Invention
The present invention relates to a digital-to-analog converter (DAC). More particularly, the present invention relates to a digital-to-analog converter of multi-level pulse width modulation.
2. Description of Related Art
Pulse width modulation (PWM) is a representation by converting pulse code modulation (PCM) using different duty cycles. By transforming the PCM into the PWM, the PWM can directly drive speakers for generating analog signals for output, which becomes a PWM DAC. The resolution, sampling rat, and input clock frequency of the PWM DAC have the following relationships:                a. resolution×sampling rate=input clock frequency, for one-end PWM DAC        b. resolution×sampling rate=2×input clock frequency, for one-end PWM DAC        
Accordingly, as the input clock frequency is fixed, the resolution is inversely proportion to the sampling rate. Namely, it has to lower the sampling rate if a high resolution of the PWM DAC is required. In contrast, it has to reduce the resolution of the PWM DAC if a high sampling rate is required.
FIG. 1 shows a conventional PWM DAC block diagram. As soon as the PCM DAC receives a PCM signal, signals P+ 12 and P− 14 are outputted to output buffers 16, 18 and then the output buffers 16, 18 output driving signals to an output device 20 such that the output signals of the output device 20 are PWM signals.
Referring to FIG. 2, the conventional PWM DAC comprises a first output driver 22 and a second output driver 24. The input of the first output driver 22 receives an input signal P+, and the output of the first output driver 22 is connected to an input of a speaker 26. The input of the second output driver 24 receives an input signal P−, and the output of the second output driver 24 is connected to another input of a speaker 26. The speaker 26 can output a sound signal to external in response to the two input signals P+ and P−. For example, the PWM DAC can receive n-bit PCM signal, and output an m-level analog signals. In addition, the input signals P+ and P− are used for converting (n-m) most significant bits (MSBs) of the n-bit PWM signal into a PWM waveform, wherein n and m are integers, and n>m.
Referring to FIG. 1, the output PWM waveforms of the first and the second output drivers 22, 24 contains only two logic levels of “0” and “1”. Because the smallest unit is 1 for the digital output of the PWM, only integers like X, X+1, and X+2 (X is an integer), etc can be represented according to the conventional method. However, if the PCM values need to be represented by fractional values like X, X+¼, X+ 2/4, and X+¾, etc, the conventional PWM DAC fails to achieve this purpose.